This invention relates to reliable high resolution patterning techniques and more particularly to the fabrication of small contact openings in large-scale-integrated (LSI) devices.
Opening very small contact windows in a relatively thick insulating layer to gain access to an underlying region is a significant problem and sometimes a limiting factor in making LSI devices such as metal-oxide-semiconductor (MOS) random access memories. Some standard MOS LSI devices include, for example, a one-micron-thick insulating layer through which the contact openings must be made. Wet chemical etching is commonly used to open windows in this insulating layer, with a patterned positive resist serving as the etching mask. But, due to undercutting during the wet etching process, it has been found difficult in practice to delineate contact windows smaller than about 4-by-4 microns.
Standard plasma etching techniques are also available for forming contact windows in LSI devices. But, since a suitable plasma-etch-resistant positive electron resist is not presently available, plasma etching is not a feasible technique for making contact windows while directly processing devices by high-resolution electron lithography. Moreover, even if such an electron resist were available, the insulating layer to be plasma etched is so relatively thick that achieving high resolution therein via a patterned resist layer is exceedingly difficult.
Accordingly, efforts have been directed at trying to devise alternative techniques capable of making very small contact windows in LSI devices in a highly reliable manner. It was recognized that the availability of such techniques, particularly if included in a high-resolution electron lithography process, would significantly advance the art of making LSI devices.